To increase storage capacity in semiconductor integrated circuit dynamic random access memories (DRAMs), trench capacitors are being widely explored. Nearly all published reports have employed trenches formed in bulk or in regions doped of a given type consistent throughout the wafer. For example, see K. Minegishi, et al. "A Submicron CMOS Megabit Level Dynamic RAM Technology Using Doped Face Trench Capacitor Cell,"Tech. Digest, IEEE IEDM, July, 1983, pp. 319-322 and J. Yamada, et al. "A Submicron 1 Mbit Dynamic RAM with a 4-Bit-at-a-Time Built-In ECC Circuit," IEEE Journal of Solid-State Circuits, Vol. SC-19, No. 5, October, 1984, pp.627-633.
Placing a trench in a well in the opposite type of substrate produces better soft error protection and lower junction leakage (the diffusion component) in the subsequently made devices because the number of minority carriers that are available to discharge the dynamic nodes are only those available within the well dimension which is small compared to the minority carrier diffusion lengths, which are relatively large.
A major problem in placing a trench in a well of the opposite type of conductivity is the fact that only a small amount of charge (due to well doping under the trench) is available to electrically isolate the trench inversion layer or capacitor electrode layer from the substrate.
As an example, consider a p-channel metal-oxidesemiconductor (PMOS) trench capacitor in an n-type well in a p-type substrate as illustrated in FIG. 1. Of course, similar arguments apply for an NMOS trench capacitor in a p-type well in an n-type substrate. In FIG. 1, semiconductor trench capacitors 10 are formed in n-type well 12 adjacent to p-type well 14 in p-type substrate 16. Throughout this application it should be realized that the prior art structures and the structures of the instant invention also work equally well in trenches in p-wells and in trenches in wells of the same conductivity type as the substrate. Capacitors 10 have plates 18 which may be polysilicon and are formed over capacitor dielectric layers 20 and p.sup.+ regions 22. Depletion region 24 forms the lateral punchthrough path between the p.sup.+ regions 18 of the two capacitors 10 shown.
Envision the p.sup.+ regions 22 of capacitors 10 cell potentials at V.sub.DD (e.g. 5V), the n well 12 at V.sub.BB (e.g. +7.5 V) and the p substrate 16 at V.sub.SS (e.g. 0V). Both the cell to well and well to substrate junctions are reverse biased. The cells 10 can punchthrough to the substrate 16 if insufficient doping exists in the well 12 below the trenches 10, that is between the p.sup.+ cell doping regions 22 to the p substrate 16. Also, resistance below and between trench capacitors such as 10 can be very high, thus degrading performance of the circuit.
In addition, for trench capacitors that are placed close to each other, lateral punchthrough currents can exist in depletion region 24 between or below the trench capacitors 10 where the well doping is light, i.e. where cell to cell depletion regions can touch.
Typically, the trench capacitors 10 of FIG. 1 may be formed by the steps illustrated in FIG. 2. A semiconductor substrate 26 is provided with isolation regions 28 between which a trench 30 is formed, as by reactive ion etching (RIE) for example, via mask pattern 32 shown in FIG. 2A. FIG. 2B illustrates a doped glass layer 34 which is deposited over the exposed surface of the substrate 26 even over the interior surfaces of trench 30. The substrate 26 is then put through a thermal cycle which partially diffuses the dopant into partial region 36. After the doped glass layer 34 is removed as seen in FIG. 2C, the dopant is further thermally diffused to form final dopant region 37. For more information, see the Minegishi, et al. and the Yamada, et al. articles cited above.
To avoid the problems caused by forming trench devices in shallow, lightly doped wells, two approaches are available. First, a heavily doped n well can be utilized to provide sufficient doping below and between trench capacitors. This approach is not advantageous because the performance of the PMOS devices in the heavily doped n well will be compromised.
Alternatively, if a moderately doped well were desired to prevent deleterious effects on PMOS performance, a very deep well is needed to produce sufficient charge below the trench capacitor and between adjacent capacitors. Such a deep well would require long thermal cycles to drive in the well impurity deeply below the trench.
However, for reasonable net charges below the cell electrode (excluding depletion regions) of about 2.times.10.sup.12 ions/cm.sup.2 and reasonable trench depths of 3 microns, for example, a moderately doped well (not lightly doped) would have to be about 8 microns deep, which is unusually deep. Some of the major disadvantages of such deep wells include large lateral diffusion, hence large separations would be required between PMOS and NMOS transistors thus eliminating the compactness advantage of the trench technology, and also a thick epitaxial layer would be required to keep the heavily doped substrate from diffusing up into the epitaxial layer. Also, a large transition distance between the lightly doped epitaxial layer and the substrate boundary would be required to prevent degradation of latchup protection due to large vertical up diffusion from the substrate.
These disadvantages conflict with providing latchup immunity with epitaxy, which requires thin epitaxial layers and short transition distances, as well as soft error protection since the deeper well produces a larger volume for minority carrier generation to discharge dynamic nodes. In addition, larger volumes produce more minority carrier diffusion current, which is also deleterious to charge storage in dynamic nodes.
High capacitance planar capacitors formed by double-diffusing n and p.sup.+ layers are described by K. Terada, et al., in "A New VLSI Memory Cell Using Capacitance Coupling (CC Cell)," IEEE Transactions on Electron Devices, Vol. ED-31, No. 9, September, 1984, pp. 1319-1324.